Discrete time (DT) filters, which can be used to implement software defined radio (SDR), allows for the support of different wireless standards. DT filters replace receiver blocks such as a mixer, a RF (radio frequency) baseband filter and amplifier, and enjoy inherent tunability which arises from sampling.
DT receivers usually include DT finite impulse response (FIR) filters to decimate an input sample rate. The DT FIR filter can be understood as an analog version of the digital FIR filter. For a digital FIR filter, each output value is a weighted sum of the successive input values as illustrated in FIG. 1.
To implement similar function in the analog domain, DT filters use multiple numbers of a sampling unit 200 shown in FIG. 2. Each unit 200 comprises one capacitor 202 and at least three switches 204, 206 and 208. The sample switch 204 implements time delay. FIR coefficients are implemented by the ratio of the capacitor 202 with the capacitor 202 of one or more other sampling units 200. Summation is achieved by connecting the capacitors 202 using the transfer switch 208. Finally, the capacitor 202 is reset by the reset switch 206 for the next input stream.
The frequency response of a typical DT filter is shown in FIG. 3, where fs is the input sample rate. Curve FIR1 plots the frequency response of a 4-tap moving average filter (coefficient [1 1 1 1]), which is chosen as the example for further discussion. To increase filter rejection, the order may be increased, as shown in dotted curve FIR2.
In H. Seo et. al., “A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1165-1174, May 2012, increasing filter order is done by cascading. In R. Bagheri et. al., “An 800-MHz-6-GHz Software-Defined Wireless Receiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2860-2875, December 2006, increasing filter order is done by increasing the number of coefficients. Both of these approaches result in significant increase in hardware complexity. As a consequence, chip area and cost of fabrication increases. In addition, the complex filter circuit comes with complex routings which bring increases in parasitic resistance and capacitance, which are not desired for high frequency/high accuracy filter design. The work of H. Seo et. al. and R. Bagheri et. al. is discussed in further detail below.
In H. Seo et. al., filter order is increased by cascading DT FIR filters. The first filter should be a non-decimation filter, because the sample rate should be maintained for the following filter to again perform identical filtering. Implementing the non-decimation filter results in a complex circuit (not shown, but see FIG. 9 of H. Seo et. al.). The total number of sampling units to implement 2nd order sinc filter [1 1 1 1]2 is 40 for a single-ended signal, of which 32 sampling units are for implementing the non-decimation filter and 8 units are for implementing a decimation filter. If the tap number is generalized as N, the complexity in H. Seo et. al. isComplexity in H. Seo et. al.=2×N2+2×N  (1),
where the numeral “2” is related to interleaving. The complexity increases with 2nd order function of N.
Instead of cascading, which results in 2nd order complexity, R. Bagheri et. al. increases the filter order by adding more filter tap. First, the 2nd order coefficient is unfolded as[1 1 1 1]2=[1 1 1 1]*[1 1 1 1]=[1 2 3 4 3 2 1]  (2),
where convolution (*) is used. Therefore, a 7 tap filter can replace cascaded non-decimation/decimation filters. If the tap number is generalized as N, the complexity for the approach used in R. Bagheri et. al. isComplexity in R. Bagheri et. al.=2×(2×N−1)  (3),
where the first numeral “2” is related to interleaving and the second numeral “2” is related to convolution. The complexity increases with 1st order function but the number of tap is doubled by the convolution. This increase in the number of tap can be visualized as shown in FIG. 4, in which 1st and 2nd order sinc diagrams of R. Bagheri et. al. are shown.
There is thus a need to provide an implementation method for DT FIR filters, whose filter order is increased without increasing the hardware complexity.